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note: this is a summary document. the complete document is available under nda. for more information, please contact your local atmel sales office. features ? supported frequency ranges ? low-band 310mhz to 318mhz, 418mhz to 477mhz ? high-band 836mhz to 928mhz ? 315.00mhz/433.92mhz/868.3 0mhz and 915.00mhz with one 24.305mhz crystal ? low current consumption ? 9.3ma for rxmode (low-band) 480a for 50ms cycle 3 channel polling ? 9.1ma/13.8ma for txmode (low -band, pout = 6dbm/10dbm) ? typical offmode current of 5na (max. 600na at vs = 3.6v and t = 85c) ? programmable output power ?12dbm to +14.5dbm (0.4db step) ? input 1db comp ression point ? ?35dbm (full sensitivity level) ? ?20dbm (15db reduced sensitivity) ? programmable channel frequency with fractional-n pll ? 93hz resolution for low-band ? 185hz resolution for high-band ? fsk deviation 0.375khz to 93khz ? fsk sensitivity (manchester coded) at 433.92mhz ? ?106dbm at 20kbit/s, f = 20khz, bw if = 165khz ? ?109dbm at 10kbit/s, f = 10khz, bw if = 165khz ? ?112dbm at 5kbit/s, f = 5khz, bw if = 165khz ? ?121dbm at 0.75kbit/s, f = 0.75khz, bw if = 25khz ? ask sensitivity (manches ter coded) at 433.92mhz ? ?107dbm at 20kbit/s, bw if = 366khz ? ?117dbm at 1kbit/s, bw if = 366khz ? programmable rx-if bandwidth 25khz to 366khz (approx. 10% steps) ? blocking (bw if = 165khz): 64dbc at freq. offset = 1mhz and 48dbc at 225khz ? high image rejection 55db (315mhz/433.92mhz) 47db (8 68.3mhz/915mhz) without calibration ? supported buffered data rate 0.5kbit/s to 20kbit/s (higher data rates up to 80kbit/s manchester coded and 160kbit/s nrz with transparent data in/output) ? supports pattern based wake-up an d start of frame identification ? digital rssi with very high relative accuracy of 1db du e to digitized if processing ? programmable clock output derived from crystal frequency ? 24kb rom with atmel firmware and integrated avr ? microcontroller for control ? 6kb in system self programmable flash for an additional customer application software ? 512 byte eeprom data memory for trans ceiver configuratio n and 768 byte sram ? spi interface for rx/tx data acces s and transceiver configuration ? configurable event signal indicates the status of the ic ? automatic antenna tuning at tx center frequency for loop antenna ? automatic low power channel polling (3 rke channels, tpms, rs) ? id scanning up to 18 di fferent ids with 1..4 byte ? supply voltage ranges 1.9v to 3.6v and 4.5v to 5.5v ? temperature range ?40c to +105c ? esd protection at all pins ( 4kv hbm, 200v mm, 750v fcdm) ? small 5mm 5mm qfn32 package/pitch 0.5mm ? suitable for applications governed by en 300 220 and fcc part 15, title 47 uhf ask/fsk transceiver atmel ATA5830 ATA5830n summary 9208ds?rke?07/11
2 9208ds?rke?07/11 atmel ATA5830/ATA5830n 1. general product description 1.1 overview the atmel ? ATA5830 is a highly integrated, low power uhf ask/fsk rf-transceiver. the atmel ATA5830 is partitioned into several sections; an rf frontend, a digital baseband, and a low power 8 bit avr microcontroller. the product is designed for the ism frequency bands in the ranges of 310 to 318mhz, 418 to 477mhz and 836 to 928mhz. external part count is kept to a minimum due to the very high level of integration in this device. by combining outstanding rf performance with highly sophisticated baseband signal processing, robust wireless com- munication can be easily achieved. the rece ive path uses a low-if architecture with an integrated double quadrature receiver and digitized if processing. this results in high image rejection and excellent blocking performance. the transmit path uses a closed loop frac- tional-n modulator with gaussian shaping and preemphasis functionality for high data rates. in addition, the highly flexible and configurable baseband signal processing allows the trans- ceiver to operate in several scanning, wake-up and automatic self polling scenarios. for example, during polling the ic can seek certain message content (ids) and save valid tele- gram data in the fifo buffer for later retrieval. the device possess two receive paths that enable parallel search for two telegrams with different modulations, data rates, wake-up condi- tions, etc. the highly configurable and autonom ous scanning capability enables polling of up to five application channels such as 3-channel rke, tpms, peg. the configuration of the transceiver is stored in a 512 byte eeprom. the spi allows for external control and reconfig- uration of the device. the internal microcontroller and 6 kb flash can be used to add customer extensions to the atmel firmware. the debug wire and isp interface are available for programming purposes. 1.2 target applications the transceiver is designed to be used in the following application areas: ? remote keyless entry system (rke) ? passive entry go system (peg) ? tire pressure monitori ng system (tpm,tpms) ? remote start system (rs) ? remote control system, e.g. garage door open ? smart rf applications ? telemetering systems three applications with a total of 5 channels are supported by the atmel firmware for autono- mous self polling.
3 9208ds?rke?07/11 atmel ATA5830/ATA5830n 1.3 main extended features of the atmel ATA5830 1.3.1 rf performance the atmel ? ATA5830 provides high sensitivity and programmable transmit power up to 14dbm. the high image rejection and outs tanding blocking performance enable a robust application against interferer with a low cost design. in addition, the programmable channel fil- ter bandwidth provides flexibility to adapt to various syst em requirements. 1.3.2 automatic self polling and multi channel capability the autonomous self polling supports the automatic scanning for three different applications such as remote keyless entry (rke), tire pressure monitoring system (tpms) and remote start (rs) using one ic. additionally multi channel systems with up to three frequencies can be scanned. this mean s five frequencies can be scanned in the autonomous polling scheme; three for rke, one for tpms and one for rs. the configuration of each application is indepen- dent of the others. this is possible because of the flexibility in the digital baseband and two different baseband receiving paths. the ic can immediately scan all applications upon power-up without the need for any initial configuration by an external microcontroller. 1.3.3 wake-up scenario and id scanning the powerful baseband signal processing is designed to offload these time consuming tasks from the host controller. this allows the transceiver to discard unwanted telegrams and limit external microcontroller wake up to valid telegrams only. up to 7 criteria can be used to deter- mine the telegram validity from carrier check on the lowest level to start of frame id pattern match at the highest level. 1.3.4 two parallel receiving paths the transceiver?s baseband contains two data paths. the parameters of both paths can be set differently, e.g. the modulation type or data rate. generally both paths are working simultane- ously but only the first path detecting a valid te legram will be used for further data reception and filling of the 32 byte buffer. the 32 byte receive data buffer can be accessed using spi commands from the external host microcontroller. 1.3.5 channel statistic in order to accelerate the communication in multi channel applications the atmel ATA5830 offers a feature defined as channel statistic. if this feature is selected , the ic will find the best channel within the three rke channels (with regard to interference) and automatically select the best channel for the first transmission. 1.3.6 antenna tuning and spdt for applications using a loop antenna, the atmel ATA5830 offers an automatic antenna tuning feature which improves the antenna performa nce by compensating for ?hand effects? or matching component value variations. the integr ated spdt acts as rx/tx switch which elim- inates the cost of an external rx/tx switch.
4 9208ds?rke?07/11 atmel ATA5830/ATA5830n 1.3.7 customer application software all the functionality is implemented in 24kb of rom firmware and controlled by spi com- mands. in addition, 6kb of flash is availa ble to enable customer specific software functionality. examples for flash customizatio n are a) extension of spi commands, b) usage of a single wire interface instead of spi, c) polling adaptations, d) protocol handling, etc. to achieve customer specific functionality, parts of the rom code can be replaced with flash code. 1.3.8 eeprom configuration the configuration of the device e.g. rf-frequency, modulation type, data rate, etc. is stored in 512kb of eeprom that is integrated within the atmel ? ATA5830. this improves the efficiency of the spi control since most of the configur ation comes from the eeprom. in most applica- tions, only the received or transmitted data and short spi commands are required. the device is delivered with a standard configuration; onl y deviations from that need to be configured. device configuration uses only a part of the 512kb of eeprom leavi ng free space available for additional customer data storage. 1.4 pin diagram and confi guration of atmel ATA5830 figure 1-1. pin diagram note: the exposed die pad is connected to the internal die. rfin_lb rfin_hb agnd pb7 pb6 pb5 pb4 pb 3 pc2 pc1 pc0 v s avcc xtal2 xtal1 te s t_en s pdt_rx s pdt_ant ant_tune s pdt_tx rf_out v s _pa pb2 3 2 1 2 expo s ed die p a d 3 4 5 6 7 8 24 2 3 22 21 20 19 1 8 17 3 1 3 0292 8 27 26 25 9 1011121 3 14 15 16 pb1 pb0 dgnd dvcc pc5 pc4 pc 3 atmel ata5 83 0 at e s t_io2 at e s t_io1
5 9208ds?rke?07/11 atmel ATA5830/ATA5830n table 1-2. pin configuration pin no. pin name type description 1 rfin_lb analog rxmode, lna input for low-band frequency range (< 500mhz) 2 rfin_hb analog rxmode, lna input for high-band frequency range (> 500mhz) 3 spdt_rx analog rxmode output of the spdt switch (damped signal output) 4 spdt_ant analog antenna input (rxmode) and output (txmode) of the spdt switch 5 ant_tune analog antenna tuning input 6 spdt_tx analog txmode input of the spdt switch 7 rfout analog power amplifier output 8 vs_pa analog power amplifier supply - 3v application supply voltage input - 5v application internal voltage regulator output 9 test_en - test enable, connected to gnd in application 10 xtal1 analog crystal oscillator pin1 (input) 11 xtal2 analog crystal oscillator pin2 (output) 12 avcc analog rf frontend supply regulator output 13 vs analog main supply voltage input 14 pc0 digital main: avr port c0 alternate: pcint8/nreset/debug wire 15 pc1 digital main: avr port c1 alternate: npwron1/pcint9 16 pc2 digital main: avr port c2 alternate: npwron2/pcint10/trpa 17 pc3 digital main: avr port c3 alternate: npwron3/pcint11/tmdo/txd 18 pc4 digital main: avr port c4 alternate: npwron4/pcint12/int0/ tmdi/rxd 19 pc5 digital main: avr port c5 alternate: npwron5/pcint13/trpb/ tmdo_clk 20 dvcc - digital supply voltage regulater output 21 dgnd - digital ground 22 pb0 digital main: avr port b0 alternate: pcint0/clk_out 23 pb1 digital main: avr port b1 alternate: pcint1 / sck 24 pb2 digital main: avr port b2 alternate: pcint2/mosi (master out slave in) 25 pb3 digital main: avr port b3 alternate: pcint3/miso (master in slave out) 26 pb4 digital main: avr port b4 alternate: pwron/pcint4/led1 (strong high side driver) 27 pb5 digital main: avr port b5 alternate: pcint5/nss 28 pb6 digital main: avr port b6 alternate: pcint6/event (firmware c ontrolled external microcontroller event flag)
6 9208ds?rke?07/11 atmel ATA5830/ATA5830n 29 pb7 digital main: avr port b7 alternate: npwron6/pcint7/ rx_active (strong high side driver)/ led0 (strong low side driver) 30 agnd - analog ground 31 atest_io2 - rf frontend test input/output 2, connected to gnd in application 32 atest_io1 - rf frontend test input/output 1, connected to gnd in application gnd - ground/backplane on exposed die pad table 1-2. pin configuration (continued) pin no. pin name type description
7 9208ds?rke?07/11 atmel ATA5830/ATA5830n 1.5 typical application circuits figure 1-1. typical 3v application with external microcontroller figure 1-1 shows a key fob application circuit with an external host microcontroller for 315mhz or 433.92mhz running from a 3v lithium cell. the atmel ? ATA5830 stays in offmode until nss(pb5) and npwron1(pc1) are used to wake it. in offmode the atmel ATA5830 draws typically less than 5na (600na maximum at 3.6v/85c). in offmode all atmel ? ATA5830 avr ? ports pb0..pb7 and pc0..p c5 are switched to input. pc0..pc5 and pb7 have internal pull-up resistors ensuring that the voltage at these ports is vs. pb0..pb6 are tristate inputs and require additional consideration. pb1,pb2 and pb5 have defined voltages since they are connected to the output of the external microcontroller. pb4 is connected to ground to avoid unwanted power ups. pb0, pb3 and pb6 do not require external circuitry since the internal circuit avoids transverse currents in the offmode. the external microcontroller has to tolerate the floating inputs. otherwise additional pull down resistors are required on these floating lines. typically, the key fob buttons are connected to the external microcontroller and the atmel ATA5830 wake-up is done by pu lling nss (pin 27) and npwron1 (pin 15) to ground. if there are not enough ports for button inputs on the microcontroller, it is possible to connect up to four additional buttons to the ports pc2..pc5. in this case, the occurrence of a port event (but- ton pressed) will generate an interrupt (pin 28). the port event that triggered the interrupt is available in the event register. rfin_lb irq n ss mi s o mo s i s ck vdd clk_in at e s t _io1 at e s t _io2 te s t _en rfin_hb agnd pb7 pb6 pb5 pb4 pb 3 pc2 pc1 pc0 v s avcc xtal2 xtal1 s pdt_rx s pdt_ant ant_tune s pdt_tx rf_out v s _pa pb2 3 2 1 2 3 4 5 6 7 8 24 2 3 22 21 20 19 1 8 17 3 1 3 0292 8 27 26 25 91011121 3 14 15 16 pb1 pb0 dgnd dvcc pc5 pc4 pc 3 v s = 3 v microcontroller atmel ata5 83 0
8 9208ds?rke?07/11 atmel ATA5830/ATA5830n in this type of application a pcb trace loop an tenna is typically used. an internal antenna tun- ing procedure tunes the resonant frequency of th is loop antenna to the tx frequency. this is accomplished with an integrated variable capacitor on the ant_tune pin. rf_out and rf_in are optimally matched to the spdt_tx and spdt_rx pins of the integrated rx/tx switch. the spdt_ant pin has an impedance of 50 for both the rx and tx functions. the dc output voltage of the power amplifier is required at the spdt_tx pin for proper operation. also, the rfin pin needs a dc path to ground, which is easily achieved with the matching shunt inductor. the impedance of the loop antenna is transformed to 50 with three capaci- tors, two of them external and one built into the atmel ATA5830 on the ant_tune pin. an external crystal, together with the fractional-n pll within the atmel ATA5830 is used to fix the rx and tx frequency. accurate load capacitor s for this crystal are integrated, to reduce system part count and cost. only four supply blocking capacitors are needed to decouple the different supply voltages avcc, dvcc, vs a nd vs_pa of the atmel ATA5830. the exposed die pad is the rf and analog ground of the atmel ATA5830. it is directly connected to agnd via a fused lead. for applications operating in the 868.3mhz or 915mhz frequency bands, a high band rf input is supplied, rfin_hb, and must be used instead of rfin_lb. the atmel ATA5830 is controlled using specif ic spi commands via the spi interface and an internal eeprom for applicat ion specific configuration. figure 1-3. typical 3v stand alone application rfin_lb at e s t _io1 te s t _io2 te s t _en rfin_hb agnd pb7 pb6 pb5 pb4 pb 3 pc2 pc1 pc0 v s avcc xtal2 xtal1 s pdt_rx s pdt_ant ant_tune s pdt_tx rf_out v s _pa pb2 3 2 1 2 3 4 5 6 7 8 24 2 3 22 21 20 19 1 8 17 3 1 3 029 2 8 27 26 25 91011121 3 14 15 16 pb1 pb0 dgnd dvcc pc5 pc4 pc 3 v s = 3 v v s atmel ata5 83 0 v s v s
9 9208ds?rke?07/11 atmel ATA5830/ATA5830n figure 1-3 shows a stand alone key fob application circuit for 315mhz or 433.92mhz running from a 3v lithium cell. the atmel ? ATA5830 stays in offmode until one of the npwron ports pc1..pc5 are pulled to ground level and therefore waking up the circuit. the npwron ports pc1..pc5 have internal 50k pull-up resistors and can be left open if not used. application software within the 6kb flash is used to control the atmel ATA5830 together with firmware in the 24kb rom. the rf and decoupling circuitry is similar to figure 1-1 on page 7 . in this application, an led is connected to pb7 (alternatively, an additional wake-up button can be used on pb7 instead of an led). an led can also be connected to pb4. however, note the additional pull-down resistor connected in parallel that is needed to prevent trans- verse currents in offmode. this special case applies to pb4 because of its active input characteristics (pwron). figure 1-4. typical 5v application circuit with external microcontroller figure 1-4 shows a typical vehicle side application circ uit with an external host microcontroller running from a 5v voltage regulator. in contrast to the 3v application with external microcon- troller, the pin pb4 (pwron) is directly connected to vs and the atmel ? ATA5830 enters the idlemode after power on. in this configur ation the atmel ATA5830 can work autonomously while the microcontroller stays powered down to achieve low current consumption while being sensitive to rf telegrams. rfin_lb irq n ss mi s o mo s i s ck vdd clk_in at e s t _io1 at e s t _io2 te s t _en rfin_hb agnd pb7 pb6 pb5 pb4 pb 3 pc2 pc1 pc0 v s avcc xtal2 xtal1 s pdt_rx s pdt_ant ant_tune s pdt_tx rf_out v s _pa pb2 3 2 1 2 3 4 5 6 7 8 24 2 3 22 21 20 19 1 8 17 3 1 3 0292 8 27 26 25 91011121 3 14 15 16 pb1 pb0 dgnd dvcc pc5 pc4 pc 3 v s = 5v v s s aw microcontroller atmel ata5 83 0
10 9208ds?rke?07/11 atmel ATA5830/ATA5830n to achieve low current in id lemode the atmel ATA5830 can be configured in the eeprom to work with the 125khz rc oscillator (this mode is named idlemode(rc)). the atmel ATA5830 can also be configured for autonomous multi channel and multi application pollingmode(rc). the external microcontroller is notified with irq if an appropriate rf message is received. until that takes place, the atme l ATA5830 periodically switches to rxmode, checks the differ- ent channels and applications configured in the eeprom and returns to the idlemode(rc) all the while with the external host avr ? microcontroller in a deep sleep mode to achieve a low average current while being polling for valid rf messages . once a valid rf message is detected, it can be buffered within the atmel ATA5830 to allow the microcontroller time to wake-up and retrieve the buffered data. in applications that use the 4.5 to 5.5v supply (vs), it is important to note that only atmel ATA5830 ports pb0..pb7, pc0..pc5 and the exte rnal host microcontroller use this supply. the power amplifier of the atmel ATA5830 is limited to 3.6v therefore an internal ldo delivers 2.7v to 3.3v supply voltage in txmode on pin vs_pa. the capacitor on pin vs_pa is needed to stabilize this regulator and decouple t he power amplifier supply voltage. the ports pc0..pc5 have internal 50k pull-up resistors and can be left open. the ant_tune pin must be left open. as in the 3v applications, rf_out and rf_in are matched to spdt_tx and spdt_rx by absorbing the parasitics of the spdt switch into the matching network, hence the spdt_ant is a 50 rx and tx port. the impedance of the saw filter is transformed with lc matching circuits to the spdt_ant port and also to the antenna. care has to be taken to insure the transmit power going through the saw does not exceed its power handling capability. the series capacitor on pin spdt_ant is needed because the dc voltage on this pin is set to vs_pa/2 voltage in txmode and saw filters normally should not be subjected to a dc volt- age. alternatively, the saw can also be inserted between spdt_rx and rf_in. in this case, special care for spurious and harmonics of the tx signal is required.
11 9208ds?rke?07/11 atmel ATA5830/ATA5830n figure 1-2. typical 5v application circuit with one wire control figure 1-2 shows a typical vehicle side application ci rcuit running from a 5v voltage regulator delivered from the lin transceiver ata6625 device. the application can be directly connected to vehicle's wiring harness. in this case, the pin pb4 (pwron) is directly connected to vs and the atmel ? ATA5830 enters the idlemode upon power up of the ata6625 and stays there after the software in the flash asserts the en pin on ata6625 to high. the system can be completely switched on or off with a command over the one wire bus. this application is used when the external host microcontroller must be separated over a distance from the atmel ATA5830 such as systems having remote antennas integrated into window glass. in these sit- uations, the atmel ATA5830 can work autonomously and communicate to external host microcontroller on a 1 wire bus. the application software within the 6kb flash, together with 24kb rom firmware, is used for the control of the atmel ATA5830 and atmel ata6625. a simplified lin compliant physical layer can be used for one wire communication. the atmel ATA5830 does not natively support one wire commands. however, through the use of application flash software one wire com- munication can be achieved. please refer to the note in the previous example ( figure 1-4 on page 9 ) regarding the use of a 4.5 to 5.5v supply and its distribution within the atmel ? ATA5830. ports pc0..pc2 have inter- nal 50k pull-up resistors and can be left open. but, ports pb1, pb2 and pb5 must be connected to ground. the ant_tune pin has to be left open. notes about rf decoupling and supply circuitry are the same as application shown in figure 1-4 on page 9 . rfin_lb rxd txd nre s vcc lin gnd en v s atmel ata6625 lin at e s t _io1 at e s t _io2 te s t _en rfin_hb agnd pb7 pb6 pb5 pb4 pb 3 pc2 pc1 pc0 v s avcc xtal2 xtal1 s pdt_rx s pdt_ant ant_tune s pdt_tx rf_out v s _pa pb2 3 2 1 2 3 4 5 6 7 8 24 2 3 22 21 20 19 1 8 17 3 1 3 0292 8 27 26 25 91011121 3 14 15 16 pb1 pb0 dgnd dvcc pc5 pc4 pc 3 v s = 5v 12v b a ttery v s s aw atmel ata5 83 0 v s +
12 9208ds?rke?07/11 atmel ATA5830/ATA5830n 1.6 system overview figure 1-3. circuit overview figure 1-3 shows an overview of the main functional blocks of the atmel ATA5830. the control of the atmel ATA5830 is performed through the spi pins sck, mosi, miso and nss found on port b. the confi guration of the atmel at a5830 is stored in th e eeprom and a large part of the functionality is defined with the firmware located in the rom and processed using the avr ? . e.g. a spi command like ?start rxmode? uses the information located in the eeprom configures all hardware registers of the different blocks according to this information, starts then the rxmode and directs the received data to the rx buffer located in the sram. an event on port pb6 is signaled to the external microcontroller when the expected number of bytes are received. part of the eeprom content is copied to the sram during start-up of the atmel ATA5830 for faster access. care should be taken to limit eeprom r/w cycle s so that the device's maxi- mum rating is not exceeded. alternatively, the user should consider modifying the parameters in the sram. rx d s p rf frontend tx d s p rfin rfout data b u s s rc, frc o s cill a tor s port b ( 8 ) xto xtal pb (0 to 7) ( s pi) pc (0 to 5) v s avcc dvcc port c (6) avr perepher a l s avr cpu su pply re s et s ram rom fl as h eeprom
13 9208ds?rke?07/11 atmel ATA5830/ATA5830n it is important to note that pwron and npwr on pins are active in offmode. this means that even if the atmel ? ATA5830 is in offmode and the dvcc voltage is switched off, power management circuitry within the atmel ATA5830 will bias these pins with vs. avr ? ports can be used as button inputs, external lna supply voltage (rx_active), led driver, event pins, switching control for additional spdt switches, general purpose digital inputs, wake up inputs etc. some functionality of these ports is already implemented in the firmware and can be activated with eeprom config uration. other function ality is possible only through custom software residing in the 6kb flash program memory. 1.7 compatibility to the atmel uhf receiver ata5780 the transceiver atmel ATA5830 is pin compatible to the receiver ata5780. the receiver has the identical rx performance of the transceiver rx path. the difference exists in the digital block only. while extremely flexib le, the receiver operates as a statemachine and its function- ality is limited to user selectable eeprom conf iguration options. as a result, the receiver is fully compatible with th e transceiver but without the flexib ility of 6kb flash program space for custom applications.
14 9208ds?rke?07/11 atmel ATA5830/ATA5830n 2. system operation modes the scope of this section is to give an overview of the atmel ? ATA5830 supported operation modes, shown in figure 2-1 . figure 2-1. operation modes overview after connecting the supply voltage to the vs pin, the atmel ATA5830 always starts in off- mode. all internal circuits are disconnected from the power supply. therefore no spi communication is supported. the atmel ATA5830 can be woken up by activating the pwron pin or one of the npwronx pins. this triggers the power-on sequence. after firmware initial- ization the atmel ATA5830 reaches the idlemode. the idlemode is the basic system mode supporting spi communication and transitions to all other operation modes. there are two options of the idlemode to be configured in the eeprom settings: ? idlemode(rc) with low power consumption using the fast rc (frc) oscillator for processing ? idlemode(xto) with active crystal oscillator for high accuracy clock output or timing measurements the transmit mode (txmode) allows for data transmission on one of the preconfigured chan- nels for e.g. rke, tpm, rs. it is usually enabled by spi command, or directly after power-on, when selected in the eeprom setting. the receive mode (rxmode) provides data reception on one of the preconfigured channels. the precondition for data reception is a valid pr eamble. the receiver is continuously searching for a valid telegram and receives the data if all preconfigured checks are successfully passed. the rxmode is usually enabled by spi command, or directly after power-on, when selected in the eeprom setting. pollingmode txmode init done power-on wdr idlemode rxmode s y s tem initi a liz a tion offmode tcmode extr
15 9208ds?rke?07/11 atmel ATA5830/ATA5830n in pollingmode the receiver is ac tivated for a short period of time to check for a valid telegram on the selected channels. the receiver will be deactivated if no valid telegram is found and a sleep period with very low power consumption elapses. this process is repeated periodically according to the eeprom configuration. up to 5 channels and a wide range of sleep times are supported by the atmel firmware. this mode is activated via an spi command, or directly after power-on, when selected in the eeprom setting. the tune and check mode (tcmode) offers a calibration and self-checking functionality for the vco and frc oscillators as well as for the antenna tuning and polling cycle accuracy. this mode is activated via an spi command. when selected in t he eeprom settin gs the tcmode is used during system initialization after power-on. furthermore, the tcmode can be activated periodically during pollingmode. table 2-1 shows the relations between the operati on modes and its corresponding power sup- plies, clock sources and sleep mode settings. table 2-1. operation modes versus supplies and oscillators operation mode avr sleep mode dvcc avcc vs_pa xto src frc offmode - off off off off off off idlemode(rc) active mode power-down (1) on off off off off off off on on on off idlemode(xto) active mode power-down (1) on on off off on on on on off off txmode active mode on on (2) on on off rxmode active mode on off on on off pollingmode(rc) - active period - sleep period active mode power-down (1) on off off off on off on on on off pollingmode(xto) - active period - sleep period active mode power-down (1) on on off off on on on on off off notes: 1. during idlemode(rc) and idlemode(xto) the avr microcontroller will enter a sleep mode to reduce the current cons umption. the sleep mode of the microcontroller section can be defined in the eeprom . to achieve the optimum current consumption the power-down mode is recommended. 2. only activated at 5 v applications. this is selectable in the eeprom setting.
16 9208ds?rke?07/11 atmel ATA5830/ATA5830n 3. hardware description 3.1 overview figure 3-1. system block diagram figure 3-1 shows the system block diagram of atmel ? ATA5830. in rxmode the crystal oscillator (xto) together with the fractional-n pll generates the local oscillator (lo) signal.the rf signal coming either from the lowband input (rfin_lb) or high- band input (rfin_hb) is amplified by the low noise amplifier (lna) and downconverted by the mixer to the intermediate frequency (if) using t he lo signal. afterwards the if signal is sam- pled using a high resolution analog to digita l converter (adc). within the rx digital signal processing (rxdsp) the received signal from the adc is filtered by a digital channel filter and demodulated. two data receive paths are included into the rxdsp after the digital channel fil- ter. the receive path can also be configured to provide the digital output of an internal temperature sensor (temp( )). lna, mixer power amplifier rx d s p adc rf frontend rfin_lb rfin_hb rfout v s _pa s pdt_rx s pdt_ant s pdt_tx ant_tune tx d s p temp ( ? ) xto xtal1 xtal2 pb (0 to 7) data bu s pc (0 to 5) irq crc avcc dvcc v s rom avr cpu fl as heeprom s ram w a tchdog timer s rc, frc o s cill a tor s clock m a n. de bu g wire nvm controller port b ( 8 ) s pi port c (6) ss i mod u l a tor rf frontend control 16 bit timer s 2x 8 bit timer s 3 x fr a ction a l n-pll power m a n a gement s pdt d a mping antenn a t u ning
17 9208ds?rke?07/11 atmel ATA5830/ATA5830n in txmode the fractional-n pll generates the tx frequency. the power amplifier generates a programmable rf output power of ?10dbm to 14dbm on rfout. the fsk modulation is per- formed by changing the frequency setting of the fractional-n pll dynamically with the tx digital signal processing (txdsp). digital preem phasis and digital gauss filtering can be acti- vated in the txdsp for higher data rates or low occupied bandwidth. the ask modulation is performed by switching the power amplifier on and off. with the single pole double throw (spdt) switch the rf signal from the antenna is switched to rfin in rxmode and from rfout to the antenna in txmode. an adjustable capacitor and an rf leveldetector on ant_tune is used to tune the center frequency of loop antennas to reduce tolerances and capacitive proximity effects. the system is controlled by an avr ? cpu with 24kb rom, 6kb flash, 512byte eeprom, 768 byte sram and other peripherals supporting the transceiver handling. two ports pb[0..7] and pc[0..5] are available for external digital connections, e.g. the spi interface is connected to port b. the atmel ? ATA5830 is controlled by eeprom configuration and spi commands. the functional behavior is mainly determined by the firmware in the rom. it can be configured to a high degree by modifying the eeprom setti ngs. the firmware running on the avr gives access to the hardware functionality of the atmel ATA5830. extensions to this firmware can be added in the 6 kb of flash memory. the rxd sp and txdsp registers are directly accessible from the avr since these dsp?s are directly connected to the avr data bus. the rf frontend registers are programmed with an on chip se rial interface(ssi) accessing the rf frontend control. the power management contains low-dropout (ldo) regulators and reset circuits for the sup- ply voltages vs, avcc, dvcc and vs_pa of the atmel ATA5830. in offmode all the supply voltages avcc, dvcc and vs_pa (vs_pa only for 4.5v to 5.5v operation) are switched off to achieve a very low current consumption. the atmel ATA5830 can be powered up by acti- vating the pwron pin or one of the npwron1..6 pins since they are still active in offmode. the rf frontend circuits and the xto are connected to avcc, the avcc domain can be switched on and off independently from dvcc. atmel ATA5830 provides two idle modes. in idlemode(rc) only the dvcc voltage regulator, the frc and src oscillators are active and the avr uses a power down mode to achieve a low current consumption. the same power down mode can be used during the inactive phases of the pollingmo de. in idlemode(xto) the avcc volt age domain as well as the xto are activated additionally. an integrated watchdog timer is available to restart the atmel ATA5830.
18 9208ds?rke?07/11 atmel ATA5830/ATA5830n 3.2 receive path 3.2.1 overview the receive path consists of a low noise amplif ier (lna), mixer, analog-to-digital converter (adc) and a rx digital signal processor (dsp) as shown figure 3-1 on page 16 . the frac- tional-n phase locked loop (pll) and the quartz oscillator (xto) described above delivers the local oscillator frequency f lo in rxmode. the receive path is controlled wit the rf frontend registers. two separate lna inputs, one for low-band and one for high-band, are provided to obtain optimum performance matching for each frequency range and to allow multi band applica- tions. a radio frequency (rf) level detector at the lna output and a switchable damping included into single-pole double-trough (spdt) swit ch is used in the presence of large block- ers to achieve better system blocking performance. the mixer converts the received rf signal to a low intermediate frequency (if) of about 250khz. a double quadrature architecture is used for the mixer to achieve high image rejec- tion. additionally, the 3 rd order suppression of local oscillator (lo) harmonic receiving will make receiving without a frontend saw filter, for example in a car keyfob application, less critical. the adc converts the if signal into the digital domain. due to the high effective resolution (14bit) of the used adc the channel filter and rssi can be realized in the digital signal domain and no analog gain control (agc) which can lead to critical timing issues or analog filtering is required in front of the adc. this leads to a receiver frontend with good blocking performance up to the 1db compression point of the lna and mixer, and a steep digital channel filters can be used. the rx dsp performs channel filtering and conv erts the digital output signals of the adc to the baseband for demodulation. due to the digita l realization of these functions the rx dsp can be adapted to the needs of many different applications since channel bandwidth, data rate, modulation type, wake-up criteria, signal checks, clock recovery and many other proper- ties are configurable. see rx dsp description in section 3.2.2 ?rx digital signal processing (rx dsp)? on page 19 . a received signal strength indicator (rssi) value is built within the rx dsp completely in the digital signal domain allowing for a high relative rssi accuracy and a good absolute accuracy, which is only deteriorated by the gain errors of lna, mixer and adc. two independent receive paths a and b are integrated in the rx dsp after the channel filter see section 3.2.2 ?rx digital signal processing (rx dsp)? on page 19 and allow the use of different data rate, modulation type and protocol without the need to power up the receive path more than once to decide which signal should be received. this allows a much lower polling current in several applications. the integration of remote keyless entry (rke ), passive entry and go (peg) and tire pressure monitoring systems (tpm) into one module is simp lified since completely different protocols can be supported and a low polling current is ac hieved. it is even possible using different receive rf bands for different applications by using the two lna inputs. for example a tpm receiver can be realized at 433.92mhz while a peg system uses the 868mhz ism band with multi channel bidirect ional communication.
19 9208ds?rke?07/11 atmel ATA5830/ATA5830n 3.2.2 rx digital signal processing (rx dsp) the rx dsp block performs the digital signal processing, decoding and checking of the rx samples from the adc. it delivers the raw data at the trpa/b pins, the decoded data at the tmdo output and the buffered data bytes (rx byte a/b) from the rx buffer. it also provides auxiliary information about the signal like the received signal strength indication (rssi) and the frequency offset of the received signal versus the selected center frequency (rxfoa/b). figure 3-2. rx dsp overview the channel filter determines the receiver bandwidth. its output is used for both receiving paths a and b. therefore it has to be configured to be suitable for both. the receiving paths a and b are identical and consist of an ask/fsk demodulator with attached signal checks, a frame synchronizer supporting pattern based search for the telegram start and a 1 byte hard- ware buffer for received data. the receiver architecture with parallel receiving paths a and b allows for a simultaneous search for two different transmitters. the simultaneous search is supported only when the flex- ible telegram suppor t is enabled (see eeprom description). e.g. path a can be configured for an ask telegram with high data rate and path b can be con- figured for an fsk telegram with low data rate. during pollingmode both settings are applied and the check occurs simultaneou sly. this results in a shor ter active time during polling. tmdo_a tmdo_clk_a tmdo_b rxfob trpb rxfoa trpa r ss i tmdo_clk_b rx byte a rx byte b demod & check a demod & check b rx b u ffer a rx b u ffer a fr a me s ync a fr a me s ync b = = rx byte a rx byte b ch a nnel filter adc d a t a
20 9208ds?rke?07/11 atmel ATA5830/ATA5830n 3.3 transmit path 3.3.1 overview the atmel ? ATA5830 integrates a transmitter that is capable of sending data with various options: ? frequency bands 310mhz ? 318mhz, 418mhz ? 477mhz, 836mhz ? 928mhz ? data rates up to 80kbit/s manchester or 160ksym/s nrz in transparent mode ? ask or fsk modulation ? transparent or buffered mode ? gauss-shaping digital filter this section describes the hardware blocks that are integrated to perform the transmit functionality. figure 3-3 shows a block diagram of the transmit data path. figure 3-3. transmit data path the transmission data source can be selected fr om a register bit, a transparent input pin 18 (tmdi) and an internal 32 byte buffer. if ask/ook modulation is selected the data stream is used to directly switch on and off the power amplifier. the transmitted carrier frequency is set by the frequency synthesizer pll. if fsk modulation is selected the data stream is used to switch between two frequencies that are generated by the frequency synthesizer pll. the power amplifier is constantly on. to reduce the occupied bandwidth a digital gauss fi ltering can be enabled. for data rates above 20khz manchester or 40khz nrz-coding a digital pre-emphasis filter has to be enabled to compensate for the pll loop filter. tdfcr gacdivh gacdivl g auss filtering power amp pll on/off tdcr.gaen ffreq2 h/l/m f s k1 1 a s k0 00 01 10 11 0 tdcr.txm s tdcr.txmod timer mod u l a tor ffreq1 h/l/m tdcr. s fm mout4tx s o4tx pin 1 8 / tmdi tdcr.peen tx d s pan a log frontend mod u l a tion s o u rce s election tdcr. s fm tdcr. s dpu tdcr. s den pre- emph as i s filtering 1 0 1 0
21 9208ds?rke?07/11 atmel ATA5830/ATA5830n 3.4 avr controller 3.4.1 cpu core figure 3-4. cpu core overview rx d s p rf frontend rfin_lb rfin_hb rfout v s _pa s pdt_rx s pdt_ant s pdt_tx ant_tune tx d s p xto xtal1 xtal2 pb(0 to 7) data bu s pc(0 to 5) irq crc avcc dvcc v s rom avr cpu fl as h eeprom s ram w a tchdog timer s rc, frc o s cill a tor s clock m a n. de bu g wire nvm controller port b( 8 ) s pi port c(6) ss i mod u l a tor 16 bit timer s 2x 8 bit timer s 3 x power m a n a gement
22 9208ds?rke?07/11 atmel ATA5830/ATA5830n 3.4.1.1 architectural overview this section discusses the avr ? core architecture in general. the main function of the cpu core is to ensure correct program execution. th erefore it must be able to access memories, perform calculations, control peripherals, and handle interrupts. figure 3-5. architectural overview in order to maximize performance and parallelis m, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. whil e one instruction is being executed, the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program me mory is in- system reprogrammable flash memory. the fast-access register file contains 32 x 8-bit general purpose working registers with a sin- gle clock cycle access time. this allows single-cyc le arithmetic logic un it (alu) operation. in a typical alu operation, two operands are output from the register file, the operation is exe- cuted, and the result is stored back in the register file ? in one clock cycle. s t a t us a nd control interr u pt unit s pi unit 3 2 x 8 gener a l p u rpo s e regi s ter s alu d a t a b us 8 - b it d a t a s ram w a tchdog timer in s tr u ction regi s ter in s tr u ction decoder clock m a n a gement eeprom portn control line s direct addre ss ing indirect addre ss ing i/o mod u le n progr a m co u nter rom fl as h progr a m memory i/o mod u le 1
23 9208ds?rke?07/11 atmel ATA5830/ATA5830n six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address ca lculations. one of these address pointers can also be used as an address pointer for l ook up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and un conditional jump and call instructions, able to directly address the whole address space. most avr ? instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. program memory space is divided in two sectio ns, the boot program section and the applica- tion program section. both sections have dedicated lock bits for write and read/write protection. the spm (store program memory) instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address of the program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and conse- quently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the stack pointer (sp) in the reset routine (before subroutines or interrupts are executed). the sp is read/wri te accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control regis- ters, spi and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the circuit has extended i/o space from 0x60 - 0xff and sram where only the st/sts/std and ld/lds/ldd instructions can be used.
24 9208ds?rke?07/11 atmel ATA5830/ATA5830n 3.5 power management 3.5.1 overview the ic has four power domains: ? vs ? the unregulated battery voltage input. ? dvcc ? the internally regulated digital supply voltage. typical value is 1.35v. ? avcc ? the internally regula ted rf frontend and xto supply. typical value is 1.85v. ? vs_pa ? the power amplifier supply has two application modes depending on the battery voltage (vs) range: ? connected externally to the battery in 3v applications. ? generated by an internal regulator in 5v applications. the at5830 can be operated from v s = 1.9v to 3.6v (3v application) and from v s = 4.5v to 5.5v (5v application). for tx output pow ers above 10dbm applied in high band frequency ranges 836mhz to 928mhz, the minimum battery voltage is limited to 2.1v. figure 3-1. power supply management power m a n a gement (common reference, volt a ge monitor v s _pa reg u l a tor avcc reg u l a tor port b s pi port c 220nf 22nf 6 8 nf v s _pa (only 3 v oper a tion) 2.2 f avcc v s v s xtal1 ... level s hifter rfin_lb rfin_hb s pdt_rx s pdt_ant s pdt_tx rf_out ant_tune xtal2 ... ... d a t a b us pb7 pb4 pc1 pc5 dvcc reg u l a tor avr cpu, avr peripher a l s , memorie s , rxd s p, txd s p a nd frc/ s rc rf frontend a nd xto dvcc
25 9208ds?rke?07/11 atmel ATA5830/ATA5830n 5 package information 4 ordering information extended type number package remarks ATA5830-pnqw qfn32 5mm 5mm pb free ATA5830n-pnqw qfn32 5mm 5mm pb free title drawing no. rev. packa g e drawin g contact: p a ck a gedr a wing s @ a tmel.com 6.54 3 -5124.01-4 common dimen s ion s (unit of me asu re = mm) min nom note max s ymbol 2 expo s ed p a d 3 .6x 3 .6 packa g e: vqfn_5x5_ 3 2l 10/12/10 dimen s ion s in mm s pecific a tion s a ccording to din technic a l dr a wing s 0.02 0.05 0.0 a1 5 5.1 4.9 e 0.2 3 0. 3 0.16 b 0.5 b s c e 0.4 0.5 0. 3 l 3 .6 3 .75 3 .45 e2 3 .6 3 .75 3 .45 d2 5 5.1 4.9 d 0.2 0.25 0.15 a 3 0.9 1 0. 8 a top view d 3 2 1 8 pin 1 id e a 3 a a1 b l z 10:1 s ide view bottom view d2 e 3 2 25 9 17 24 16 8 1 e2 z
26 9208ds?rke?07/11 atmel ATA5830/ATA5830n 6. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 9208ds-rke-07/11 ? set datasheet from preliminary to standard 9208cs-rke-07/11 ? document completely redesigned 9208bs-rke-01/11 ? section 5 ?ordering information? on page 29 changed
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